This invention relates to digital communication systems and, more particularly, to a processor arrangement employable in such systems for increasing the run length of digital signals.
In conventional facsimile systems, a picture image includes a plurality of lines, each line having a plurality of picture elements. Usually, within a facsimile system transmitter, a coder digitally encodes a voltage which varies in amplitude with the level of brightness of sequentially scanned picture elements (pels). The encoded voltage, hereinafter called the pel signal, is transmitted to a receiver where it is decoded and a facsimile of the picture image assembled.
Often, sequential picture elements have the same brightness level. As a result, the corresponding sequential pel signals are identical. Hence, an identical signal is repetitively transmitted. The resultant repetition of signals, known in the art as a run, leads to inefficient use of the transmission link between transmitter and receiver. To mitigate against the inefficient use, various run-length coding arrangements are known. A typical run-length coder extends two quanta of data to the receiver: one, the brightness level and the other, the length of the run, e.g., a count of the number of sequential picture elements having the same brightness level. Of course, the count could be one, but as the run-length increases, more efficient use of the transmission link is possible.
Accordingly, an object of our invention is to increase the length of a run in a facsimile system.